Design a verilog model of a half adder and write a testbench to verify the designed verilog model
module Add-half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
XOR (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule
今天上課有點累，所以就一直睡覺沒練習，下次吧= =
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