10/20

odule top;
wire x_in1,x_in2,x_in3,x_in4;
wire y_out;
system_clock #100 clock1(x_in1);
system_clock #300 clock2(x_in2);
system_clock #200 clock2(x_in3);
system_clock #150 clock2(x_in4);

test AHI(y_out,x_in1,x_in2,x_in3,x_in4);

endmodule

module test(y_out,x_in1,x_in2,x_in3,x_in4);

input x_in1,x_in2,x_in3,x_in4;
output y_out;
wire y1,y2;


and #1(y1,x_in1,x_in2);
and #1(y2,x_in3,x_in4);
nor #1(y_out,y1,y2);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
#(PERIOD/4) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule


時間好快，期中考要到了

module top;
wire a,b;
wire sum,c_out;

system_clock #100 clock1(a);
system_clock #50 clock2(b);

Add_half AH1(sum,c_out,a,b);

endmodule

module Add_half(sum,c_out, a, b);

input a,b;
output sum,c_out;
wire c_out_bar;


xor(sum, a, b);
nand(c_out_bar, a, b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD = 100;
output clk;
reg clk;
initial
clk = 0;
always
begin
#(PERIOD/2) clk = ~clk;
#(PERIOD/2) clk = ~clk;
end
always@(posedge clk)
if($time > 1000) #(PERIOD-1)$stop;
endmodule

今天終於有教材了，不過搞笑的是，都印錯了= =

印到別本去了，大家都傻眼了，老師也無奈

還好老師將錯就錯，打算交叉著上

不然不管拿到哪一版本的教材都會虧

10/6

Design a verilog model of a half adder and write a testbench to verify the designed verilog model

module Add-half (sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
XOR (sum,a,b);
nand (c_out_bar,a,b);
not (c_out,c_out_bar);
endmodule

今天上課有點累，所以就一直睡覺沒練習，下次吧= =

97/09/22 上課日誌

今天上課，還好老師佛心，讓我們加簽，不然我們幾個就畢不了業了，謝謝老師。

這是今天上課的成果:D(如圖)